The present invention relates to plasma processing apparatus and methods employed for fine-patterning to-be-processed substrates such as wafers in a semiconductor manufacturing process. More particularly, the invention relates to plasma processing apparatus and methods much less susceptible to the charge-up damages.
The plasma processing techniques involving the plasma etching technique and the plasma CVD technique are widely used in the apparatus for manufacturing semiconductor devices.
FIG. 1 shows a structure of a typical plasma etching apparatus of the related art employed in plasma-etching an insulating film.
The plasma etching apparatus shown in FIG. 1 is in a so-called two-frequency capacitively coupled type structure. The processing chamber 101 includes therein a lower electrode 102 for placing thereon a substrate to be processed and an upper electrode 103 in opposition to the lower electrode 102. An etching gas such as Ar gas, fluorocarbon gas, or O2 gas is supplied into the chamber 101. A high frequency power source 104 supplies high frequency power at 200 MHz to the upper electrode 103 through a matching box 105 for generation of a plasma P. Hereafter, the high frequency power source for powering the upper electrode is referred to as “a main power source”.
Meanwhile, the lower electrode 102 is, as a bias, supplied with high frequency power at 4 MHz from another high frequency power source 106 through another matching box 107. Hereafter, the high frequency power source for powering the lower electrode is referred to as “a biasing power source”. As the biasing power source is coupled via a stopping capacitor in the matching box 107 to the lower electrode, a self bias potential (Vdc), which is at a DC negative voltage, is applied to the to-be-processed substrate W. The distance between the lower electrode 102 and upper electrode 103 will be referred to as “the gap”. Recently, in the process of manufacturing semiconductor devices for which finer patterns are always promoted, etching of an insulating film is achieved with a process called a narrow gap process in which the above-mentioned gap is narrow. Typically, the gap is as narrow as 18 mm to 30 mm or so.
When an insulating film formed on a to-be-processed substrate W is plasma-etched for patterning with the related art plasma etching apparatus, a problem arises such that, some devices in the substrate may be damaged during the plasma etching to lower the production yield, particularly so when the gap is narrow. This phenomenon is called the charge-up damage. In this specification, it will be merely referred to as “the damage”.
FIG. 2 shows a structure of a device called “the antenna MOS capacitor type damage TEG (Test Element Group)”, which serves to determine damages.
The device has a gate oxide film and a gate electrode formed on a Si substrate in the described order, the Si substrate being a to-be-processed substrate. When the potential difference between the gate electrode and the Si substrate exceeds a blocking voltage of the gate oxide film, electric current will flow through the gate oxide film to cause a dielectric breakdown. Whether the dielectric breakdown is reached or not may be known from a corresponding change in the current-voltage characteristics of the device. Thus, by providing such a device in a surface of a to-be-processed substrate, it will be possible to detect locations of damages having occurred.
When a semiconductor device to be subjected to the plasma etching treatment includes a structure similar to that of the antenna MOS capacitor type damage TEG, occurrence of a dielectric breakdown to damage the semiconductor device will lead to a lowering of the production yield. Such damage is caused by a potential difference between the gate electrode and the Si substrate, the potential difference being considered to be brought about by a non-uniformity of the in-plane distribution of the Vdc applied to the to-be-processed substrate.
The potential of the Si substrate is determined by a mean value of Vdc applied to the whole Si substrate, while the potential of the gate electrode is determined by Vdc applied to the gate electrode. Therefore, when the in-plane distribution of Vdc is not uniform, a difference is apt to occur between Vdc applied to the gate electrode and the potential of the Si substrate so that damages are liable to take place.
On the contrary, when the in-plane distribution of Vdc is uniform, damages are not liable to take place. Various measures have heretofore been studied and investigated for suppressing the damages, and JP-A-2001-156051 corresponding to U.S. Pat. No. 6,426,477, for example, discloses a process in which, at the time of igniting/quenching a plasma, a biasing power source is rendered to have some output with a sheath existing, thereby effecting the plasma ignition/quenching.